The communication of digital signals over wires and cables gives rise to a number of problems. Some of these problems arise when communicating information between circuits on different printed circuit boards over a backplane, or even over the short distances traversed between circuits on a single circuit board. Transmission line effects are one such problem. In fact, in the context of the fastest ECL chips with rise times of less than one nanosecond, these effects are so severe that signal lines of more than one inch must be treated as transmission lines and be properly terminated to avoid impedance mismatch and signal reflection.
At the output pin of an integrated circuit, an output buffer is typically needed to transfer signals to the signal lines. The term "buffer" may also refer to an entire IC dedicated solely to driving the signal lines. An output buffer 100 coupled to a transmission line 102 is illustrated in FIG. 1. The transmission line has a characteristic impedance Z.sub.0. The output buffer 100 includes an ideal buffer 104. The "real world" output buffer 100 exhibits an output impedance R.sub.LH 106 when the output undergoes a low-to-high transition, and an output impedance R.sub.HL 108 when undergoing a high-to-low transition. These impedances are, for the most part, contributed by pull-up and pull-down transistors at the output stage of the buffer.
FIG. 2 illustrates the output of the buffer 100 (assumed to be noninverting) as it undergoes a transition from a high state (typically on the order of 3 volts) to a low state (typically 0 volts). It can be seen that a high-to-low input does not necessarily produce a sharp transition at the output. Rather, the output waveform exhibits an intermediate step before falling to the low state. This step is caused by the fact that for a high-to-low transition, the resistor R.sub.HL is in series with the characteristic impedance Z.sub.0 and acts as a voltage divider. The height of the step depends on the relative values of R.sub.HL and Z.sub.0 and the length of the step depends upon the roundtrip electrical delay of the output signal through the transmission line.
The input buffer of another circuit that receives the output waveform may malfunction in response to the step. Further, it is known that the step input into one end of a transmission line may cause an apparent signal skew between the two ends.
The transition step is not the only transmission line effect on the buffer output. As is well-known in the art, if the output impedance of the buffer is not closely matched to the characteristic impedance of the transmission line, then the output waveform will experience undershoot and overshoot, i.e., ringing, when it approaches its final value. On the other hand, if the output impedance is matched to the transmission line impedance during much of the step, then the buffer may not be able to sink or source a sufficient DC current if the transmission line is of low impedance or has some form of DC termination.
One can thus appreciate the desirability of eliminating both the transition step and impedance mismatch effects caused by the interface of an output buffer with a transmission line.
Other examples of output buffers may be found in, for example, U.S. Pat. No. 5,528,166, which provides a pulse controlled impedance compensated output buffer utilizing two drivers which are activated during a portion of the switching time of the output. The two drivers are activated for different durations which partially encompass the output transition. U.S. Pat. No. 5,457,407 provides a reference circuit having a plurality of reference transistors connected in parallel to each other and an output driver circuit having a corresponding plurality of driver transistors connected in parallel with each other. The transistors in the reference circuit are selectively connected in order to match an impedance of the reference transistors to the impedance of a user selected resistor, representing a fraction of the impedance of the transmission line. The selection of the reference transistors also determines the selection of the driver transistors and, as a result, causes the impedance of the output driver to match the impedance of the transmission line. U.S. Pat. No. 5,448,182 provides a driver circuit having a high impedance driver and a low impedance driver connected to the near end of a transmission line. A sensing circuit determines when a predetermined voltage is reached and provides a control signal to deactivate the low impedance driver. As a result, a limited self-adjusting impedance matching is provided. U.S. Pat. No. 5,559,477 provides an output buffer with a variable output impedance so that the output impedance is set relatively low during the initial portion of an output transition.